module CPSCrypto
#(
  parameter CORE_BUS_WIDTH = 32,
  parameter CORE_ADDR      = 4
)(
  //OUTPUTS
  output [CORE_BUS_WIDTH - 1:0] PRDATA,         //APB Read Bus
  output PREADY,                                //APB Ready Signal
  output PSLVERR,                               //APB Error Signal
  output INT_CRYPTO,                            //Interruption Signal
  //INPUTS
  input [CORE_BUS_WIDTH - 1:0] PWDATA,          //APB Write Bus
  input [CORE_ADDR - 1:0] PADDR,                //APB Address Bus
  input PSEL,                                   //APB Select Signal
  input PENABLE,                                //APB Enable Signal
  input PWRITE,                                 //APB Read/Write Signal
  input PCLK,                                   //APB Clock
  input PRESETn                                 //APB Reset 
);

  wire [CORE_BUS_WIDTH - 1:0] bus_rd, bus_wr;
  wire [CORE_ADDR - 1:0] addr;
  wire busy_n, write_en, read_en;
  
  aes_core CORE
  (
    .bus_rd       ( bus_rd       ),
    .interrupt    ( INT_CRYPTO   ),
    .busy_n       ( busy_n       ),
    .bus_wr       ( bus_wr       ),
    .write_en     ( write_en     ),
    .read_en      ( read_en      ),
    .addr         ( addr         ),
    .clk          ( PCLK         ),
    .rst_n        ( PRESETn      )
  );
  
  apb_to_core
  #(
    .CORE_BUS_WIDTH ( CORE_BUS_WIDTH ),
    .CORE_ADDR      ( CORE_ADDR      )
  )
   APB
  (
    .PRDATA        ( PRDATA   ),
    .PREADY        ( PREADY   ),      
    .PSLVERR       ( PSLVERR  ),     
    .core_bus_wr   ( bus_wr   ),  
    .core_write_en ( write_en ),
    .core_read_en  ( read_en  ),
    .core_addr     ( addr     ),  
    .PWDATA        ( PWDATA   ),     
    .PADDR         ( PADDR    ),      
    .PSEL          ( PSEL     ),       
    .PENABLE       ( PENABLE  ),    
    .PWRITE        ( PWRITE   ),     
    .PCLK          ( PCLK     ),       
    .PRESETn       ( PRESETn  ),    
    .core_bus_rd   ( bus_rd   ),
    .core_busy_n   ( busy_n   ) 
  );
endmodule
